[all-commits] [llvm/llvm-project] cf277f: [M68k][NFC] Coalesce render methods in different a...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf277f0b31df14a0800b6cd30c37b76528cdd520
      https://github.com/llvm/llvm-project/commit/cf277f0b31df14a0800b6cd30c37b76528cdd520
  Author: Min-Yih Hsu <minyihh at uci.edu>
  Date:   2021-08-09 (Mon, 09 Aug 2021)

  Changed paths:
    M llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
    M llvm/lib/Target/M68k/M68kInstrInfo.td

  Log Message:
  -----------
  [M68k][NFC] Coalesce render methods in different asm register op class

And assign RegClass (i.e. operand class for all GPR) as the super class
of ARegClass and DRegClass. Note that this is a NFC change because
actually we already had XRDReg to model either address or data register
operands (as well as test coverage for it). The new super class syntax
added here is just making the relations between three RegClass-es more
explicit.


  Commit: 7cbcde4aa302135a78417aa0435f9da71a62137d
      https://github.com/llvm/llvm-project/commit/7cbcde4aa302135a78417aa0435f9da71a62137d
  Author: Min-Yih Hsu <minyihh at uci.edu>
  Date:   2021-08-09 (Mon, 09 Aug 2021)

  Changed paths:
    M llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
    M llvm/lib/Target/M68k/M68kInstrInfo.td
    R llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir
    R llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBcc.mir
    R llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxCALL.mir
    A llvm/test/MC/M68k/Control/Classes/MxBRA.s
    A llvm/test/MC/M68k/Control/Classes/MxBcc.s
    A llvm/test/MC/M68k/Control/Classes/MxCALL.s

  Log Message:
  -----------
  [M68k] Use separate asm operand class for different widths of address

This could help asm parser to pick the correct variant of instruction.
This patch also migrated all the control instructions MC tests.


Compare: https://github.com/llvm/llvm-project/compare/1a18bb9270ce...7cbcde4aa302