Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: cd2594e1c67836bfeb8dd416ac32c77abba3f290
https://github.com/llvm/llvm-project/commit/cd2594e1c67836bfeb8dd416ac32c77abba3f290
Author: Jay Foad <jay.foad at amd.com>
Date: 2021-08-06 (Fri, 06 Aug 2021)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
Log Message:
-----------
[GlobalISel] Improve legalization of narrow CTTZ
Differential Revision: https://reviews.llvm.org/D107457
Commit: d77b43c385276536c48c02761d7149e0dbad5aae
https://github.com/llvm/llvm-project/commit/d77b43c385276536c48c02761d7149e0dbad5aae
Author: Jay Foad <jay.foad at amd.com>
Date: 2021-08-06 (Fri, 06 Aug 2021)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
Log Message:
-----------
[AMDGPU][GlobalISel] Add G_AMDGPU_FFBL_B32
This is the counterpart to G_AMDGPU_FFBH_U32 which already exists. These
instructions have a defined result of -1 when the input is zero.
Differential Revision: https://reviews.llvm.org/D107441
Commit: 24b67a9024cc1a757466b4a40c05b4fd8e4b3c69
https://github.com/llvm/llvm-project/commit/24b67a9024cc1a757466b4a40c05b4fd8e4b3c69
Author: Jay Foad <jay.foad at amd.com>
Date: 2021-08-06 (Fri, 06 Aug 2021)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Improve regbankselect for 64-bit VGPR ctlz_zero_undef/cttz_zero_undef
We can improve on the generic splitting by using ffbh/ffbl, which have a
defined result when the input is zero.
Differential Revision: https://reviews.llvm.org/D107442
Commit: 83610d4eb025c07c311c4ff73accac53e21cf759
https://github.com/llvm/llvm-project/commit/83610d4eb025c07c311c4ff73accac53e21cf759
Author: Jay Foad <jay.foad at amd.com>
Date: 2021-08-06 (Fri, 06 Aug 2021)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttz
Differential Revision: https://reviews.llvm.org/D107474
Compare: https://github.com/llvm/llvm-project/compare/62fc3e0ad6e4...83610d4eb025