[all-commits] [llvm/llvm-project] f7076c: [DAGCombiner][RISCV][AMDGPU] Call SimplifyDemanded...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7076cfd3ad39ac71314c2deb5c5517c7c6bfd61
      https://github.com/llvm/llvm-project/commit/f7076cfd3ad39ac71314c2deb5c5517c7c6bfd61
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-05 (Thu, 05 Aug 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV][AMDGPU] Call SimplifyDemandedBits at the end of visitMULHU to enable known bits contant folding.

We don't have real demanded bits support for MULHU, but we can
still use the known bits based constant folding support at the end
of SimplifyDemandedBits to simplify a MULHU. This helps with cases
where we know the LHS and RHS have enough leading zeros so that
the high multiply result is always 0.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D106471