[all-commits] [llvm/llvm-project] 31a71a: [WebAssembly] Make result of 'catch' inst variadic
Heejin Ahn via All-commits
all-commits at lists.llvm.org
Wed Aug 4 14:05:59 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 31a71a393f65d9e07b5b0756fef9dd16690950ee
https://github.com/llvm/llvm-project/commit/31a71a393f65d9e07b5b0756fef9dd16690950ee
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2021-08-04 (Wed, 04 Aug 2021)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISD.def
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
Log Message:
-----------
[WebAssembly] Make result of 'catch' inst variadic
`catch` instruction can have any number of result values depending on
its tag, but so far we have only needed a single i32 return value for
C++ exception so the instruction was specified that way. But using the
instruction for SjLj handling requires multiple return values.
This makes `catch` instruction's results variadic and moves selection of
`throw` and `catch` instruction from ISelLowering to ISelDAGToDAG.
Moving `catch` to ISelDAGToDAG is necessary because I am not aware of
a good way to do instruction selection for variadic output instructions
in TableGen. This also moves `throw` because 1. `throw` and `catch`
share the same utility function and 2. there is really no reason we
should do that in ISelLowering in the first place. What we do is mostly
the same in both places, and moving them to ISelDAGToDAG allows us to
remove unnecessary mid-level nodes for `throw` and `catch` in
WebAssemblyISD.def and WebAssemblyInstrInfo.td.
This also adds handling for new `catch` instruction to AsmTypeCheck.
Reviewed By: dschuff, tlively
Differential Revision: https://reviews.llvm.org/D107423
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