[all-commits] [llvm/llvm-project] 2f43c8: [DivRemPairs] make sure we have a valid CFG for ho...

[RotateRight via All-commits]

  Branch: refs/heads/release/13.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f43c816f18a4e953e07b9d2be663b9509b7a342
      https://github.com/llvm/llvm-project/commit/2f43c816f18a4e953e07b9d2be663b9509b7a342
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-08-02 (Mon, 02 Aug 2021)

  Changed paths:
    M llvm/lib/Transforms/Scalar/DivRemPairs.cpp
    M llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll

  Log Message:
  -----------
  [DivRemPairs] make sure we have a valid CFG for hoisting division

This transform was added with e38b7e894808ec2
and as shown in:
https://llvm.org/PR51241
...it could crash without an extra check of the blocks.

There might be a more compact way to write this constraint,
but we can't just count the successors/predecessors without
affecting a test that includes a switch instruction.

(cherry picked from commit 5b83261c1518a39636abe094123f1704bbfd972f)


  Commit: e6ca0238335b5b4b52a8e5af8233bfe6d6aa7bb1
      https://github.com/llvm/llvm-project/commit/e6ca0238335b5b4b52a8e5af8233bfe6d6aa7bb1
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-08-02 (Mon, 02 Aug 2021)

  Changed paths:
    M llvm/test/CodeGen/AArch64/addsub.ll
    M llvm/test/CodeGen/X86/combine-add.ll

  Log Message:
  -----------
  [AArch64][x86] add tests for add-with-overflow folds; NFC

There's a generic combine for these, but no test coverage.
It's not clear if this is actually a good fold.
The combine was added with D58874, but it has a bug that
can cause crashing ( https://llvm.org/PR51238 ).

(cherry picked from commit e427077ec10ea18ac21f5065342183481d87783a)


  Commit: 3bce61312d4636ef6fd9e46c8d84e3fefba0569a
      https://github.com/llvm/llvm-project/commit/3bce61312d4636ef6fd9e46c8d84e3fefba0569a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-08-02 (Mon, 02 Aug 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/addsub.ll
    M llvm/test/CodeGen/X86/combine-add.ll

  Log Message:
  -----------
  [DAGCombiner] don't try to partially reduce add-with-overflow ops

This transform was added with D58874, but there were no tests for overflow ops.
We need to change this one way or another because it can crash as shown in:
https://llvm.org/PR51238

Note that if there are no uses of an overflow op's bool overflow result, we
reduce it to a regular math op, so we continue to fold that case either way.
If we have uses of both the math and the overflow bool, then we are likely
not saving anything by creating an independent sub instruction as seen in
the test diffs here.

This patch makes the behavior in SDAG consistent with what we do in
instcombine AFAICT.

Differential Revision: https://reviews.llvm.org/D106983

(cherry picked from commit fa6b2c9915ba27e1e97f8901ea4aa877f331fb9f)


Compare: https://github.com/llvm/llvm-project/compare/9ac5717f9de6...3bce61312d46