[all-commits] [llvm/llvm-project] f6c44c: [NFC][InstCombine] Add tests for xor reductions on...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6c44cdd3773a74fe52127b78c494d07f909e74d
      https://github.com/llvm/llvm-project/commit/f6c44cdd3773a74fe52127b78c494d07f909e74d
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-08-02 (Mon, 02 Aug 2021)

  Changed paths:
    A llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll

  Log Message:
  -----------
  [NFC][InstCombine] Add tests for xor reductions on i1 elt type (PR51259)


  Commit: 1e801439be26569c9ede6fd309a645b00adb656c
      https://github.com/llvm/llvm-project/commit/1e801439be26569c9ede6fd309a645b00adb656c
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-08-02 (Mon, 02 Aug 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    M llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll

  Log Message:
  -----------
  [InstCombine] `xor` reduction w/ i1 elt type is a parity check

For i1 element type, `xor` and `add` are interchangeable
(https://alive2.llvm.org/ce/z/e77hhQ), so we should treat it just like
an `add` reduction and consistently transform them both:
https://alive2.llvm.org/ce/z/MjCm5W (self)
https://alive2.llvm.org/ce/z/kgqF4M (skipped zext)
https://alive2.llvm.org/ce/z/pgy3HP (skipped sext)

Though, let's emit the IR that is similar to the one we produce for
`vector_reduce_add(<n x i1>)`.

See https://bugs.llvm.org/show_bug.cgi?id=51259


Compare: https://github.com/llvm/llvm-project/compare/8490a7d908a9...1e801439be26