[all-commits] [llvm/llvm-project] 29b263: [Clang][AArch64] Inline assembly support for the A...

[Alexandros Lamprineas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 29b263a34f1afbae9c95bf48eab7e8aac8132a80
      https://github.com/llvm/llvm-project/commit/29b263a34f1afbae9c95bf48eab7e8aac8132a80
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-07-31 (Sat, 31 Jul 2021)

  Changed paths:
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/CodeGen/CGStmt.cpp
    M clang/lib/CodeGen/TargetInfo.cpp
    M clang/lib/CodeGen/TargetInfo.h
    A clang/test/CodeGen/aarch64-ls64-inline-asm.c

  Log Message:
  -----------
  [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'

In LLVM IR terms the ACLE type 'data512_t' is essentially an aggregate
type { [8 x i64] }. When emitting code for inline assembly operands,
clang tries to scalarize aggregate types to an integer of the equivalent
length, otherwise it passes them by-reference. This patch adds a target
hook to tell whether a given inline assembly operand is scalarizable
so that clang can emit code to pass/return it by-value.

Differential Revision: https://reviews.llvm.org/D94098


  Commit: 3094e5389b3dfb046eebcb549f7f4b814258863e
      https://github.com/llvm/llvm-project/commit/3094e5389b3dfb046eebcb549f7f4b814258863e
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-07-31 (Sat, 31 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  [AArch64] Add a Machine Value Type for 8 consecutive registers

Adds MVT::i64x8, a Machine Value Type needed for lowering inline assembly
operands which materialize a sequence of eight general purpose registers.

Differential Revision: https://reviews.llvm.org/D94096


  Commit: 7d940432c46be83b8fcb5dbefee439585fa820cd
      https://github.com/llvm/llvm-project/commit/7d940432c46be83b8fcb5dbefee439585fa820cd
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-07-31 (Sat, 31 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    A llvm/test/CodeGen/AArch64/ls64-inline-asm.ll

  Log Message:
  -----------
  [AArch64] Legalize MVT::i64x8 in DAG isel lowering

This patch legalizes the Machine Value Type introduced in D94096 for loads
and stores. A new target hook named getAsmOperandValueType() is added which
maps i512 to MVT::i64x8. GlobalISel falls back to DAG for legalization.

Differential Revision: https://reviews.llvm.org/D94097


Compare: https://github.com/llvm/llvm-project/compare/fb09f365ae28...7d940432c46b