[all-commits] [llvm/llvm-project] f19226: GlobalISel: Have load lowering handle some unalign...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f19226dda5aea6d677b0e52b309ef9c605178a51
      https://github.com/llvm/llvm-project/commit/f19226dda5aea6d677b0e52b309ef9c605178a51
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-07-30 (Fri, 30 Jul 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir

  Log Message:
  -----------
  GlobalISel: Have load lowering handle some unaligned accesses

The code for splitting an unaligned access into 2 pieces is
essentially the same as for splitting a non-power-of-2 load for
scalars. It would be better to pick an optimal memory access size and
directly use it, but splitting in half is what the DAG does.

As-is this fixes handling of some unaligned sextload/zextloads for
AMDGPU. In the future this will help drop the ugly abuse of
narrowScalar to handle splitting unaligned accesses.