[all-commits] [llvm/llvm-project] 3a349d: [AArch64][SME] Introduce feature for streaming mode
Cullen Rhodes via All-commits
all-commits at lists.llvm.org
Fri Jul 30 01:00:12 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 3a349d22692c0deb7a5fc5a242886d7d6f428d6e
https://github.com/llvm/llvm-project/commit/3a349d22692c0deb7a5fc5a242886d7d6f428d6e
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/test/MC/AArch64/SME/revd.s
M llvm/test/MC/AArch64/SME/sclamp.s
M llvm/test/MC/AArch64/SME/uclamp.s
M llvm/test/MC/AArch64/SVE/abs.s
M llvm/test/MC/AArch64/SVE/add.s
M llvm/test/MC/AArch64/SVE/addpl.s
M llvm/test/MC/AArch64/SVE/addvl.s
M llvm/test/MC/AArch64/SVE/and.s
M llvm/test/MC/AArch64/SVE/ands.s
M llvm/test/MC/AArch64/SVE/andv.s
M llvm/test/MC/AArch64/SVE/asr.s
M llvm/test/MC/AArch64/SVE/asrd.s
M llvm/test/MC/AArch64/SVE/asrr.s
M llvm/test/MC/AArch64/SVE/bfcvt.s
M llvm/test/MC/AArch64/SVE/bfcvtnt.s
M llvm/test/MC/AArch64/SVE/bfdot.s
M llvm/test/MC/AArch64/SVE/bfmlal.s
M llvm/test/MC/AArch64/SVE/bfmmla.s
M llvm/test/MC/AArch64/SVE/bic.s
M llvm/test/MC/AArch64/SVE/bics.s
M llvm/test/MC/AArch64/SVE/brka.s
M llvm/test/MC/AArch64/SVE/brkas.s
M llvm/test/MC/AArch64/SVE/brkb.s
M llvm/test/MC/AArch64/SVE/brkbs.s
M llvm/test/MC/AArch64/SVE/brkn.s
M llvm/test/MC/AArch64/SVE/brkns.s
M llvm/test/MC/AArch64/SVE/brkpa.s
M llvm/test/MC/AArch64/SVE/brkpas.s
M llvm/test/MC/AArch64/SVE/brkpb.s
M llvm/test/MC/AArch64/SVE/brkpbs.s
M llvm/test/MC/AArch64/SVE/clasta.s
M llvm/test/MC/AArch64/SVE/clastb.s
M llvm/test/MC/AArch64/SVE/cls.s
M llvm/test/MC/AArch64/SVE/clz.s
M llvm/test/MC/AArch64/SVE/cmpeq.s
M llvm/test/MC/AArch64/SVE/cmpge.s
M llvm/test/MC/AArch64/SVE/cmpgt.s
M llvm/test/MC/AArch64/SVE/cmphi.s
M llvm/test/MC/AArch64/SVE/cmphs.s
M llvm/test/MC/AArch64/SVE/cmple.s
M llvm/test/MC/AArch64/SVE/cmplo.s
M llvm/test/MC/AArch64/SVE/cmpls.s
M llvm/test/MC/AArch64/SVE/cmplt.s
M llvm/test/MC/AArch64/SVE/cmpne.s
M llvm/test/MC/AArch64/SVE/cnot.s
M llvm/test/MC/AArch64/SVE/cnt.s
M llvm/test/MC/AArch64/SVE/cntb.s
M llvm/test/MC/AArch64/SVE/cntd.s
M llvm/test/MC/AArch64/SVE/cnth.s
M llvm/test/MC/AArch64/SVE/cntp.s
M llvm/test/MC/AArch64/SVE/cntw.s
M llvm/test/MC/AArch64/SVE/compact.s
M llvm/test/MC/AArch64/SVE/cpy.s
M llvm/test/MC/AArch64/SVE/ctermeq.s
M llvm/test/MC/AArch64/SVE/ctermne.s
M llvm/test/MC/AArch64/SVE/decb.s
M llvm/test/MC/AArch64/SVE/decd.s
M llvm/test/MC/AArch64/SVE/dech.s
M llvm/test/MC/AArch64/SVE/decp.s
M llvm/test/MC/AArch64/SVE/decw.s
M llvm/test/MC/AArch64/SVE/dup.s
M llvm/test/MC/AArch64/SVE/dupm.s
M llvm/test/MC/AArch64/SVE/eon.s
M llvm/test/MC/AArch64/SVE/eor.s
M llvm/test/MC/AArch64/SVE/eors.s
M llvm/test/MC/AArch64/SVE/eorv.s
M llvm/test/MC/AArch64/SVE/ext.s
M llvm/test/MC/AArch64/SVE/fabd.s
M llvm/test/MC/AArch64/SVE/fabs.s
M llvm/test/MC/AArch64/SVE/facge.s
M llvm/test/MC/AArch64/SVE/facgt.s
M llvm/test/MC/AArch64/SVE/facle.s
M llvm/test/MC/AArch64/SVE/faclt.s
M llvm/test/MC/AArch64/SVE/fadd.s
M llvm/test/MC/AArch64/SVE/fadda.s
M llvm/test/MC/AArch64/SVE/faddv.s
M llvm/test/MC/AArch64/SVE/fcadd.s
M llvm/test/MC/AArch64/SVE/fcmeq.s
M llvm/test/MC/AArch64/SVE/fcmge.s
M llvm/test/MC/AArch64/SVE/fcmgt.s
M llvm/test/MC/AArch64/SVE/fcmla.s
M llvm/test/MC/AArch64/SVE/fcmle.s
M llvm/test/MC/AArch64/SVE/fcmlt.s
M llvm/test/MC/AArch64/SVE/fcmne.s
M llvm/test/MC/AArch64/SVE/fcmuo.s
M llvm/test/MC/AArch64/SVE/fcpy.s
M llvm/test/MC/AArch64/SVE/fcvt.s
M llvm/test/MC/AArch64/SVE/fcvtzs.s
M llvm/test/MC/AArch64/SVE/fcvtzu.s
M llvm/test/MC/AArch64/SVE/fdiv.s
M llvm/test/MC/AArch64/SVE/fdivr.s
M llvm/test/MC/AArch64/SVE/fdup.s
M llvm/test/MC/AArch64/SVE/fexpa.s
M llvm/test/MC/AArch64/SVE/fmad.s
M llvm/test/MC/AArch64/SVE/fmax.s
M llvm/test/MC/AArch64/SVE/fmaxnm.s
M llvm/test/MC/AArch64/SVE/fmaxnmv.s
M llvm/test/MC/AArch64/SVE/fmaxv.s
M llvm/test/MC/AArch64/SVE/fmin.s
M llvm/test/MC/AArch64/SVE/fminnm.s
M llvm/test/MC/AArch64/SVE/fminnmv.s
M llvm/test/MC/AArch64/SVE/fminv.s
M llvm/test/MC/AArch64/SVE/fmla.s
M llvm/test/MC/AArch64/SVE/fmls.s
M llvm/test/MC/AArch64/SVE/fmov.s
M llvm/test/MC/AArch64/SVE/fmsb.s
M llvm/test/MC/AArch64/SVE/fmul.s
M llvm/test/MC/AArch64/SVE/fmulx.s
M llvm/test/MC/AArch64/SVE/fneg.s
M llvm/test/MC/AArch64/SVE/fnmad.s
M llvm/test/MC/AArch64/SVE/fnmla.s
M llvm/test/MC/AArch64/SVE/fnmls.s
M llvm/test/MC/AArch64/SVE/fnmsb.s
M llvm/test/MC/AArch64/SVE/frecpe.s
M llvm/test/MC/AArch64/SVE/frecps.s
M llvm/test/MC/AArch64/SVE/frecpx.s
M llvm/test/MC/AArch64/SVE/frinta.s
M llvm/test/MC/AArch64/SVE/frinti.s
M llvm/test/MC/AArch64/SVE/frintm.s
M llvm/test/MC/AArch64/SVE/frintn.s
M llvm/test/MC/AArch64/SVE/frintp.s
M llvm/test/MC/AArch64/SVE/frintx.s
M llvm/test/MC/AArch64/SVE/frintz.s
M llvm/test/MC/AArch64/SVE/frsqrte.s
M llvm/test/MC/AArch64/SVE/frsqrts.s
M llvm/test/MC/AArch64/SVE/fscale.s
M llvm/test/MC/AArch64/SVE/fsqrt.s
M llvm/test/MC/AArch64/SVE/fsub.s
M llvm/test/MC/AArch64/SVE/fsubr.s
M llvm/test/MC/AArch64/SVE/ftmad.s
M llvm/test/MC/AArch64/SVE/ftsmul.s
M llvm/test/MC/AArch64/SVE/ftssel.s
M llvm/test/MC/AArch64/SVE/incb.s
M llvm/test/MC/AArch64/SVE/incd.s
M llvm/test/MC/AArch64/SVE/inch.s
M llvm/test/MC/AArch64/SVE/incp.s
M llvm/test/MC/AArch64/SVE/incw.s
M llvm/test/MC/AArch64/SVE/index.s
M llvm/test/MC/AArch64/SVE/insr.s
M llvm/test/MC/AArch64/SVE/lasta.s
M llvm/test/MC/AArch64/SVE/lastb.s
A llvm/test/MC/AArch64/SVE/ld1b-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1b.s
A llvm/test/MC/AArch64/SVE/ld1d-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1d.s
A llvm/test/MC/AArch64/SVE/ld1h-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1h.s
M llvm/test/MC/AArch64/SVE/ld1rb.s
M llvm/test/MC/AArch64/SVE/ld1rd.s
M llvm/test/MC/AArch64/SVE/ld1rh.s
M llvm/test/MC/AArch64/SVE/ld1rqb.s
M llvm/test/MC/AArch64/SVE/ld1rqd.s
M llvm/test/MC/AArch64/SVE/ld1rqh.s
M llvm/test/MC/AArch64/SVE/ld1rqw.s
M llvm/test/MC/AArch64/SVE/ld1rsb.s
M llvm/test/MC/AArch64/SVE/ld1rsh.s
M llvm/test/MC/AArch64/SVE/ld1rsw.s
M llvm/test/MC/AArch64/SVE/ld1rw.s
A llvm/test/MC/AArch64/SVE/ld1sb-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1sb.s
A llvm/test/MC/AArch64/SVE/ld1sh-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1sh.s
A llvm/test/MC/AArch64/SVE/ld1sw-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1sw.s
A llvm/test/MC/AArch64/SVE/ld1w-sve-only.s
M llvm/test/MC/AArch64/SVE/ld1w.s
M llvm/test/MC/AArch64/SVE/ld2b.s
M llvm/test/MC/AArch64/SVE/ld2d.s
M llvm/test/MC/AArch64/SVE/ld2h.s
M llvm/test/MC/AArch64/SVE/ld2w.s
M llvm/test/MC/AArch64/SVE/ld3b.s
M llvm/test/MC/AArch64/SVE/ld3d.s
M llvm/test/MC/AArch64/SVE/ld3h.s
M llvm/test/MC/AArch64/SVE/ld3w.s
M llvm/test/MC/AArch64/SVE/ld4b.s
M llvm/test/MC/AArch64/SVE/ld4d.s
M llvm/test/MC/AArch64/SVE/ld4h.s
M llvm/test/MC/AArch64/SVE/ld4w.s
M llvm/test/MC/AArch64/SVE/ldff1b.s
M llvm/test/MC/AArch64/SVE/ldff1d.s
M llvm/test/MC/AArch64/SVE/ldff1h.s
M llvm/test/MC/AArch64/SVE/ldff1sb.s
M llvm/test/MC/AArch64/SVE/ldff1sh.s
M llvm/test/MC/AArch64/SVE/ldff1sw.s
M llvm/test/MC/AArch64/SVE/ldff1w.s
M llvm/test/MC/AArch64/SVE/ldnf1b.s
M llvm/test/MC/AArch64/SVE/ldnf1d.s
M llvm/test/MC/AArch64/SVE/ldnf1h.s
M llvm/test/MC/AArch64/SVE/ldnf1sb.s
M llvm/test/MC/AArch64/SVE/ldnf1sh.s
M llvm/test/MC/AArch64/SVE/ldnf1sw.s
M llvm/test/MC/AArch64/SVE/ldnf1w.s
M llvm/test/MC/AArch64/SVE/ldnt1b.s
M llvm/test/MC/AArch64/SVE/ldnt1d.s
M llvm/test/MC/AArch64/SVE/ldnt1h.s
M llvm/test/MC/AArch64/SVE/ldnt1w.s
M llvm/test/MC/AArch64/SVE/ldr.s
M llvm/test/MC/AArch64/SVE/lsl.s
M llvm/test/MC/AArch64/SVE/lslr.s
M llvm/test/MC/AArch64/SVE/lsr.s
M llvm/test/MC/AArch64/SVE/lsrr.s
M llvm/test/MC/AArch64/SVE/mad.s
M llvm/test/MC/AArch64/SVE/matrix-multiply-fp32.s
M llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s
M llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s
M llvm/test/MC/AArch64/SVE/mla.s
M llvm/test/MC/AArch64/SVE/mls.s
M llvm/test/MC/AArch64/SVE/mov.s
M llvm/test/MC/AArch64/SVE/movprfx.s
M llvm/test/MC/AArch64/SVE/movs.s
M llvm/test/MC/AArch64/SVE/msb.s
M llvm/test/MC/AArch64/SVE/mul.s
M llvm/test/MC/AArch64/SVE/nand.s
M llvm/test/MC/AArch64/SVE/nands.s
M llvm/test/MC/AArch64/SVE/neg.s
M llvm/test/MC/AArch64/SVE/nor.s
M llvm/test/MC/AArch64/SVE/nors.s
M llvm/test/MC/AArch64/SVE/not.s
M llvm/test/MC/AArch64/SVE/nots.s
M llvm/test/MC/AArch64/SVE/orn.s
M llvm/test/MC/AArch64/SVE/orns.s
M llvm/test/MC/AArch64/SVE/orr.s
M llvm/test/MC/AArch64/SVE/orrs.s
M llvm/test/MC/AArch64/SVE/orv.s
M llvm/test/MC/AArch64/SVE/pfalse.s
M llvm/test/MC/AArch64/SVE/pfirst.s
M llvm/test/MC/AArch64/SVE/pnext.s
A llvm/test/MC/AArch64/SVE/prfb-sve-only.s
M llvm/test/MC/AArch64/SVE/prfb.s
A llvm/test/MC/AArch64/SVE/prfd-sve-only.s
M llvm/test/MC/AArch64/SVE/prfd.s
A llvm/test/MC/AArch64/SVE/prfh-sve-only.s
M llvm/test/MC/AArch64/SVE/prfh.s
A llvm/test/MC/AArch64/SVE/prfw-sve-only.s
M llvm/test/MC/AArch64/SVE/prfw.s
M llvm/test/MC/AArch64/SVE/ptest.s
M llvm/test/MC/AArch64/SVE/ptrue.s
M llvm/test/MC/AArch64/SVE/ptrues.s
M llvm/test/MC/AArch64/SVE/punpkhi.s
M llvm/test/MC/AArch64/SVE/punpklo.s
M llvm/test/MC/AArch64/SVE/rbit.s
M llvm/test/MC/AArch64/SVE/rdffr.s
M llvm/test/MC/AArch64/SVE/rdffrs.s
M llvm/test/MC/AArch64/SVE/rdvl.s
M llvm/test/MC/AArch64/SVE/rev.s
M llvm/test/MC/AArch64/SVE/revb.s
M llvm/test/MC/AArch64/SVE/revh.s
M llvm/test/MC/AArch64/SVE/revw.s
M llvm/test/MC/AArch64/SVE/sabd.s
M llvm/test/MC/AArch64/SVE/saddv.s
M llvm/test/MC/AArch64/SVE/scvtf.s
M llvm/test/MC/AArch64/SVE/sdiv.s
M llvm/test/MC/AArch64/SVE/sdivr.s
M llvm/test/MC/AArch64/SVE/sdot.s
M llvm/test/MC/AArch64/SVE/sel.s
M llvm/test/MC/AArch64/SVE/setffr.s
M llvm/test/MC/AArch64/SVE/smax.s
M llvm/test/MC/AArch64/SVE/smaxv.s
M llvm/test/MC/AArch64/SVE/smin.s
M llvm/test/MC/AArch64/SVE/sminv.s
M llvm/test/MC/AArch64/SVE/smulh.s
M llvm/test/MC/AArch64/SVE/splice.s
M llvm/test/MC/AArch64/SVE/sqadd.s
M llvm/test/MC/AArch64/SVE/sqdecb.s
M llvm/test/MC/AArch64/SVE/sqdecd.s
M llvm/test/MC/AArch64/SVE/sqdech.s
M llvm/test/MC/AArch64/SVE/sqdecp.s
M llvm/test/MC/AArch64/SVE/sqdecw.s
M llvm/test/MC/AArch64/SVE/sqincb.s
M llvm/test/MC/AArch64/SVE/sqincd.s
M llvm/test/MC/AArch64/SVE/sqinch.s
M llvm/test/MC/AArch64/SVE/sqincp.s
M llvm/test/MC/AArch64/SVE/sqincw.s
M llvm/test/MC/AArch64/SVE/sqsub.s
A llvm/test/MC/AArch64/SVE/st1b-sve-only.s
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A llvm/test/MC/AArch64/SVE/st1d-sve-only.s
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M llvm/test/MC/AArch64/SVE/sub.s
M llvm/test/MC/AArch64/SVE/subr.s
M llvm/test/MC/AArch64/SVE/sunpkhi.s
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M llvm/test/MC/AArch64/SVE/tbl.s
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M llvm/test/MC/AArch64/SVE/umaxv.s
M llvm/test/MC/AArch64/SVE/umin.s
M llvm/test/MC/AArch64/SVE/uminv.s
M llvm/test/MC/AArch64/SVE/umulh.s
M llvm/test/MC/AArch64/SVE/uqadd.s
M llvm/test/MC/AArch64/SVE/uqdecb.s
M llvm/test/MC/AArch64/SVE/uqdecd.s
M llvm/test/MC/AArch64/SVE/uqdech.s
M llvm/test/MC/AArch64/SVE/uqdecp.s
M llvm/test/MC/AArch64/SVE/uqdecw.s
M llvm/test/MC/AArch64/SVE/uqincb.s
M llvm/test/MC/AArch64/SVE/uqincd.s
M llvm/test/MC/AArch64/SVE/uqinch.s
M llvm/test/MC/AArch64/SVE/uqincp.s
M llvm/test/MC/AArch64/SVE/uqincw.s
M llvm/test/MC/AArch64/SVE/uqsub.s
M llvm/test/MC/AArch64/SVE/uunpkhi.s
M llvm/test/MC/AArch64/SVE/uunpklo.s
M llvm/test/MC/AArch64/SVE/uxtb.s
M llvm/test/MC/AArch64/SVE/uxth.s
M llvm/test/MC/AArch64/SVE/uxtw.s
M llvm/test/MC/AArch64/SVE/uzp1.s
M llvm/test/MC/AArch64/SVE/uzp2.s
M llvm/test/MC/AArch64/SVE/whilele.s
M llvm/test/MC/AArch64/SVE/whilelo.s
M llvm/test/MC/AArch64/SVE/whilels.s
M llvm/test/MC/AArch64/SVE/whilelt.s
M llvm/test/MC/AArch64/SVE/wrffr.s
M llvm/test/MC/AArch64/SVE/zip1.s
M llvm/test/MC/AArch64/SVE/zip2.s
M llvm/test/MC/AArch64/SVE2/adclb.s
M llvm/test/MC/AArch64/SVE2/adclt.s
M llvm/test/MC/AArch64/SVE2/addhnb.s
M llvm/test/MC/AArch64/SVE2/addhnt.s
M llvm/test/MC/AArch64/SVE2/addp.s
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/bcax.s
M llvm/test/MC/AArch64/SVE2/bdep.s
M llvm/test/MC/AArch64/SVE2/bext.s
M llvm/test/MC/AArch64/SVE2/bgrp.s
M llvm/test/MC/AArch64/SVE2/bsl.s
M llvm/test/MC/AArch64/SVE2/bsl1n.s
M llvm/test/MC/AArch64/SVE2/bsl2n.s
M llvm/test/MC/AArch64/SVE2/cadd.s
M llvm/test/MC/AArch64/SVE2/cdot.s
M llvm/test/MC/AArch64/SVE2/cmla.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/eor3.s
M llvm/test/MC/AArch64/SVE2/eorbt.s
M llvm/test/MC/AArch64/SVE2/eortb.s
M llvm/test/MC/AArch64/SVE2/ext.s
M llvm/test/MC/AArch64/SVE2/faddp.s
M llvm/test/MC/AArch64/SVE2/fcvtlt.s
M llvm/test/MC/AArch64/SVE2/fcvtnt.s
M llvm/test/MC/AArch64/SVE2/fcvtx.s
M llvm/test/MC/AArch64/SVE2/fcvtxnt.s
M llvm/test/MC/AArch64/SVE2/flogb.s
M llvm/test/MC/AArch64/SVE2/fmaxnmp.s
M llvm/test/MC/AArch64/SVE2/fmaxp.s
M llvm/test/MC/AArch64/SVE2/fminnmp.s
M llvm/test/MC/AArch64/SVE2/fminp.s
M llvm/test/MC/AArch64/SVE2/fmlalb.s
M llvm/test/MC/AArch64/SVE2/fmlalt.s
M llvm/test/MC/AArch64/SVE2/fmlslb.s
M llvm/test/MC/AArch64/SVE2/fmlslt.s
M llvm/test/MC/AArch64/SVE2/histcnt.s
M llvm/test/MC/AArch64/SVE2/histseg.s
M llvm/test/MC/AArch64/SVE2/ldnt1b.s
M llvm/test/MC/AArch64/SVE2/ldnt1d.s
M llvm/test/MC/AArch64/SVE2/ldnt1h.s
M llvm/test/MC/AArch64/SVE2/ldnt1sb.s
M llvm/test/MC/AArch64/SVE2/ldnt1sh.s
M llvm/test/MC/AArch64/SVE2/ldnt1sw.s
M llvm/test/MC/AArch64/SVE2/ldnt1w.s
M llvm/test/MC/AArch64/SVE2/match.s
M llvm/test/MC/AArch64/SVE2/mla.s
M llvm/test/MC/AArch64/SVE2/mls.s
M llvm/test/MC/AArch64/SVE2/mul.s
M llvm/test/MC/AArch64/SVE2/nbsl.s
M llvm/test/MC/AArch64/SVE2/nmatch.s
M llvm/test/MC/AArch64/SVE2/pmul.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullb.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/test/MC/AArch64/SVE2/pmullt.s
M llvm/test/MC/AArch64/SVE2/raddhnb.s
M llvm/test/MC/AArch64/SVE2/raddhnt.s
M llvm/test/MC/AArch64/SVE2/rax1.s
M llvm/test/MC/AArch64/SVE2/rshrnb.s
M llvm/test/MC/AArch64/SVE2/rshrnt.s
M llvm/test/MC/AArch64/SVE2/rsubhnb.s
M llvm/test/MC/AArch64/SVE2/rsubhnt.s
M llvm/test/MC/AArch64/SVE2/saba.s
M llvm/test/MC/AArch64/SVE2/sabalb.s
M llvm/test/MC/AArch64/SVE2/sabalt.s
M llvm/test/MC/AArch64/SVE2/sabdlb.s
M llvm/test/MC/AArch64/SVE2/sabdlt.s
M llvm/test/MC/AArch64/SVE2/sadalp.s
M llvm/test/MC/AArch64/SVE2/saddlb.s
M llvm/test/MC/AArch64/SVE2/saddlbt.s
M llvm/test/MC/AArch64/SVE2/saddlt.s
M llvm/test/MC/AArch64/SVE2/saddwb.s
M llvm/test/MC/AArch64/SVE2/saddwt.s
M llvm/test/MC/AArch64/SVE2/sbclb.s
M llvm/test/MC/AArch64/SVE2/sbclt.s
M llvm/test/MC/AArch64/SVE2/shadd.s
M llvm/test/MC/AArch64/SVE2/shrnb.s
M llvm/test/MC/AArch64/SVE2/shrnt.s
M llvm/test/MC/AArch64/SVE2/shsub.s
M llvm/test/MC/AArch64/SVE2/shsubr.s
M llvm/test/MC/AArch64/SVE2/sli.s
M llvm/test/MC/AArch64/SVE2/sm4e.s
M llvm/test/MC/AArch64/SVE2/sm4ekey.s
M llvm/test/MC/AArch64/SVE2/smaxp.s
M llvm/test/MC/AArch64/SVE2/sminp.s
M llvm/test/MC/AArch64/SVE2/smlalb.s
M llvm/test/MC/AArch64/SVE2/smlalt.s
M llvm/test/MC/AArch64/SVE2/smlslb.s
M llvm/test/MC/AArch64/SVE2/smlslt.s
M llvm/test/MC/AArch64/SVE2/smulh.s
M llvm/test/MC/AArch64/SVE2/smullb.s
M llvm/test/MC/AArch64/SVE2/smullt.s
M llvm/test/MC/AArch64/SVE2/splice.s
M llvm/test/MC/AArch64/SVE2/sqabs.s
M llvm/test/MC/AArch64/SVE2/sqadd.s
M llvm/test/MC/AArch64/SVE2/sqcadd.s
M llvm/test/MC/AArch64/SVE2/sqdmlalb.s
M llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
M llvm/test/MC/AArch64/SVE2/sqdmlalt.s
M llvm/test/MC/AArch64/SVE2/sqdmlslb.s
M llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
M llvm/test/MC/AArch64/SVE2/sqdmlslt.s
M llvm/test/MC/AArch64/SVE2/sqdmulh.s
M llvm/test/MC/AArch64/SVE2/sqdmullb.s
M llvm/test/MC/AArch64/SVE2/sqdmullt.s
M llvm/test/MC/AArch64/SVE2/sqneg.s
M llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
M llvm/test/MC/AArch64/SVE2/sqrdmlah.s
M llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
M llvm/test/MC/AArch64/SVE2/sqrdmulh.s
M llvm/test/MC/AArch64/SVE2/sqrshl.s
M llvm/test/MC/AArch64/SVE2/sqrshlr.s
M llvm/test/MC/AArch64/SVE2/sqrshrnb.s
M llvm/test/MC/AArch64/SVE2/sqrshrnt.s
M llvm/test/MC/AArch64/SVE2/sqrshrunb.s
M llvm/test/MC/AArch64/SVE2/sqrshrunt.s
M llvm/test/MC/AArch64/SVE2/sqshl.s
M llvm/test/MC/AArch64/SVE2/sqshlr.s
M llvm/test/MC/AArch64/SVE2/sqshlu.s
M llvm/test/MC/AArch64/SVE2/sqshrnb.s
M llvm/test/MC/AArch64/SVE2/sqshrnt.s
M llvm/test/MC/AArch64/SVE2/sqshrunb.s
M llvm/test/MC/AArch64/SVE2/sqshrunt.s
M llvm/test/MC/AArch64/SVE2/sqsub.s
M llvm/test/MC/AArch64/SVE2/sqsubr.s
M llvm/test/MC/AArch64/SVE2/sqxtnb.s
M llvm/test/MC/AArch64/SVE2/sqxtnt.s
M llvm/test/MC/AArch64/SVE2/sqxtunb.s
M llvm/test/MC/AArch64/SVE2/sqxtunt.s
M llvm/test/MC/AArch64/SVE2/srhadd.s
M llvm/test/MC/AArch64/SVE2/sri.s
M llvm/test/MC/AArch64/SVE2/srshl.s
M llvm/test/MC/AArch64/SVE2/srshlr.s
M llvm/test/MC/AArch64/SVE2/srshr.s
M llvm/test/MC/AArch64/SVE2/srsra.s
M llvm/test/MC/AArch64/SVE2/sshllb.s
M llvm/test/MC/AArch64/SVE2/sshllt.s
M llvm/test/MC/AArch64/SVE2/ssra.s
M llvm/test/MC/AArch64/SVE2/ssublb.s
M llvm/test/MC/AArch64/SVE2/ssublbt.s
M llvm/test/MC/AArch64/SVE2/ssublt.s
M llvm/test/MC/AArch64/SVE2/ssubltb.s
M llvm/test/MC/AArch64/SVE2/ssubwb.s
M llvm/test/MC/AArch64/SVE2/ssubwt.s
M llvm/test/MC/AArch64/SVE2/stnt1b.s
M llvm/test/MC/AArch64/SVE2/stnt1d.s
M llvm/test/MC/AArch64/SVE2/stnt1h.s
M llvm/test/MC/AArch64/SVE2/stnt1w.s
M llvm/test/MC/AArch64/SVE2/subhnb.s
M llvm/test/MC/AArch64/SVE2/subhnt.s
M llvm/test/MC/AArch64/SVE2/suqadd.s
M llvm/test/MC/AArch64/SVE2/tbl.s
M llvm/test/MC/AArch64/SVE2/tbx.s
M llvm/test/MC/AArch64/SVE2/uaba.s
M llvm/test/MC/AArch64/SVE2/uabalb.s
M llvm/test/MC/AArch64/SVE2/uabalt.s
M llvm/test/MC/AArch64/SVE2/uabdlb.s
M llvm/test/MC/AArch64/SVE2/uabdlt.s
M llvm/test/MC/AArch64/SVE2/uadalp.s
M llvm/test/MC/AArch64/SVE2/uaddlb.s
M llvm/test/MC/AArch64/SVE2/uaddlt.s
M llvm/test/MC/AArch64/SVE2/uaddwb.s
M llvm/test/MC/AArch64/SVE2/uaddwt.s
M llvm/test/MC/AArch64/SVE2/uhadd.s
M llvm/test/MC/AArch64/SVE2/uhsub.s
M llvm/test/MC/AArch64/SVE2/uhsubr.s
M llvm/test/MC/AArch64/SVE2/umaxp.s
M llvm/test/MC/AArch64/SVE2/uminp.s
M llvm/test/MC/AArch64/SVE2/umlalb.s
M llvm/test/MC/AArch64/SVE2/umlalt.s
M llvm/test/MC/AArch64/SVE2/umlslb.s
M llvm/test/MC/AArch64/SVE2/umlslt.s
M llvm/test/MC/AArch64/SVE2/umulh.s
M llvm/test/MC/AArch64/SVE2/umullb.s
M llvm/test/MC/AArch64/SVE2/umullt.s
M llvm/test/MC/AArch64/SVE2/uqadd.s
M llvm/test/MC/AArch64/SVE2/uqrshl.s
M llvm/test/MC/AArch64/SVE2/uqrshlr.s
M llvm/test/MC/AArch64/SVE2/uqrshrnb.s
M llvm/test/MC/AArch64/SVE2/uqrshrnt.s
M llvm/test/MC/AArch64/SVE2/uqshl.s
M llvm/test/MC/AArch64/SVE2/uqshlr.s
M llvm/test/MC/AArch64/SVE2/uqshrnb.s
M llvm/test/MC/AArch64/SVE2/uqshrnt.s
M llvm/test/MC/AArch64/SVE2/uqsub.s
M llvm/test/MC/AArch64/SVE2/uqsubr.s
M llvm/test/MC/AArch64/SVE2/uqxtnb.s
M llvm/test/MC/AArch64/SVE2/uqxtnt.s
M llvm/test/MC/AArch64/SVE2/urecpe.s
M llvm/test/MC/AArch64/SVE2/urhadd.s
M llvm/test/MC/AArch64/SVE2/urshl.s
M llvm/test/MC/AArch64/SVE2/urshlr.s
M llvm/test/MC/AArch64/SVE2/urshr.s
M llvm/test/MC/AArch64/SVE2/ursqrte.s
M llvm/test/MC/AArch64/SVE2/ursra.s
M llvm/test/MC/AArch64/SVE2/ushllb.s
M llvm/test/MC/AArch64/SVE2/ushllt.s
M llvm/test/MC/AArch64/SVE2/usqadd.s
M llvm/test/MC/AArch64/SVE2/usra.s
M llvm/test/MC/AArch64/SVE2/usublb.s
M llvm/test/MC/AArch64/SVE2/usublt.s
M llvm/test/MC/AArch64/SVE2/usubwb.s
M llvm/test/MC/AArch64/SVE2/usubwt.s
M llvm/test/MC/AArch64/SVE2/whilege.s
M llvm/test/MC/AArch64/SVE2/whilegt.s
M llvm/test/MC/AArch64/SVE2/whilehi.s
M llvm/test/MC/AArch64/SVE2/whilehs.s
M llvm/test/MC/AArch64/SVE2/whilerw.s
M llvm/test/MC/AArch64/SVE2/whilewr.s
M llvm/test/MC/AArch64/SVE2/xar.s
Log Message:
-----------
[AArch64][SME] Introduce feature for streaming mode
The Scalable Matrix Extension (SME) introduces a new execution mode
called Streaming SVE mode. In streaming mode a substantial subset of the
SVE and SVE2 instruction set is available, along with new outer product,
load, store, extract and insert instructions that operate on the new
architectural register state for the matrix.
To support streaming mode this patch introduces a new subtarget feature
+streaming-sve. If enabled, the subset of SVE(2) instructions are
available. The existing behaviour for SVE(2) remains unchanged, the
subset of instructions that are legal in streaming mode are enabled if
either +sve[2] or +streaming-sve is specified. Instructions that are
illegal in streaming mode remain predicated on +sve[2].
The SME target feature has been updated to imply +streaming-sve rather
than +sve.
The following changes are made to the SVE(2) tests:
* For instructions that are legal in streaming mode:
- added RUN line to verify +streaming-sve enables the instruction.
- updated diagnostic to 'instruction requires: streaming-sve or sve'.
* For instructions that are illegal in streaming-mode:
- added RUN line to verify +streaming-sve does not enable the
instruction.
SVE(2) instructions that are legal in streaming mode have:
if !HaveSVE[2]() && !HaveSME() then UNDEFINED;
at the top of the pseudocode in the XML.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions
Reviewed By: sdesmalen, david-arm
Differential Revision: https://reviews.llvm.org/D106272
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