[all-commits] [llvm/llvm-project] 95ef46: Handle subregs and superregs in callee-saved regis...

[Jessica Clarke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 95ef464ac9d1972953709c57449ac178771cd221
      https://github.com/llvm/llvm-project/commit/95ef464ac9d1972953709c57449ac178771cd221
  Author: Jessica Clarke <jrtc27 at jrtc27.com>
  Date:   2021-07-29 (Thu, 29 Jul 2021)

  Changed paths:
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/test/CodeGen/PowerPC/fp-strict.ll
    M llvm/test/CodeGen/PowerPC/spe.ll

  Log Message:
  -----------
  Handle subregs and superregs in callee-saved register mask

If a target lists both a subreg and a superreg in a callee-saved
register mask, the prolog will spill both aliasing registers. Instead,
don't spill the subreg if a superreg is being spilled. This case is hit by the
PowerPC SPE code, as well as a modified RISC-V backend for CHERI I maintain out
of tree.

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D73170