[all-commits] [llvm/llvm-project] 54588b: [RISCV] Restrict performANY_EXTENDCombine to preve...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 54588bcc052e5b08f90e672c33d0c1ad4eda2424
      https://github.com/llvm/llvm-project/commit/54588bcc052e5b08f90e672c33d0c1ad4eda2424
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-28 (Wed, 28 Jul 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/pr51206.ll

  Log Message:
  -----------
  [RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.

The sign_extend we insert here can get turned into a zero_extend if
the sign bit is known zero. This can enable a setcc combine that
shrinks compares with zero_extend. This reduces the use count of
the zero_extend allowing other combines to turn it back into an
any_extend.

This restricts the combine to only cases where the result is used
by a CopyToReg. This works for my original motivating case. I
hope the CopyToReg use will prevent any converted extends from
turning back into an any_extend.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D106754