[all-commits] [llvm/llvm-project] 3852b8: [RISCV] Select vector shl by 1 to a vector add.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3852b8c70fbf5ad55e87ab5ccb0bd2f0a5c65977
      https://github.com/llvm/llvm-project/commit/3852b8c70fbf5ad55e87ab5ccb0bd2f0a5c65977
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Select vector shl by 1 to a vector add.

A vector add may be faster than a vector shift.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D106689