[all-commits] [llvm/llvm-project] 172487: [RISCV] Add support for vector saturating add/sub ...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 172487fe4c67dfe97d40f4dfd0992569746ae651
      https://github.com/llvm/llvm-project/commit/172487fe4c67dfe97d40f4dfd0992569746ae651
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add support for vector saturating add/sub operations

This patch adds support for lowering the saturating vector add/sub
intrinsics to RVV instructions, for both fixed-length and
scalable-vector forms alike.

Note that some of the DAG combines are still not triggering for the
scalable-vector tests. These require a bit more work in the DAGCombiner
itself.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106651