[all-commits] [llvm/llvm-project] 3b77e2: [SVE] Use reg+reg addressing mode for immediate of...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b77e2737c8545aa628e1d2cff5799db033f7081
      https://github.com/llvm/llvm-project/commit/3b77e2737c8545aa628e1d2cff5799db033f7081
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2021-07-26 (Mon, 26 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

  Log Message:
  -----------
  [SVE] Use reg+reg addressing mode for immediate offsets.

For reg+imm SVE addressing mode imm is implictly scaled by VL,
making them impractical for truely immediate offsets.  However, if
the offset can be unscaled based on the storage element type we
can use the reg+reg SVE addressing mode and thus either reduce the
number of generate add instructions or replace them with a mov
instruction that can be hoisted from the hot code path.

Differential Revision: https://reviews.llvm.org/D106744