[all-commits] [llvm/llvm-project] 73e4e9: [AArch64][SVE] Improve code generation for vector_...
CarolineConcatto via All-commits
all-commits at lists.llvm.org
Mon Jul 26 03:25:45 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 73e4e9cd007a71fb7186933abdcae024fe65cea7
https://github.com/llvm/llvm-project/commit/73e4e9cd007a71fb7186933abdcae024fe65cea7
Author: Caroline Concatto <caroline.concatto at arm.com>
Date: 2021-07-26 (Mon, 26 Jul 2021)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
Log Message:
-----------
[AArch64][SVE] Improve code generation for vector_splice for Imm == -1
This patch implements vector_splice in tablegen for:
a) when the immediate is equal to -1 (Imm==1) and uses:
INSR + LASTB
For instance :
@llvm.experimental.vector.splice(Vector_1, Vector_2, -1)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <D, E, F, G>
LAST RegLast, Vector_1 // RegLast = D
INSR Res, (Vector_1 >> 1), RegLast // Res = D + E, F, G
Differential Revision: https://reviews.llvm.org/D105633
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