[all-commits] [llvm/llvm-project] acbc0c: [AArch64][GlobalISel] Widen non-pow-2 types for sh...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acbc0c5f0ebd8b7ebfa2eb3ae77428eb83c428c5
      https://github.com/llvm/llvm-project/commit/acbc0c5f0ebd8b7ebfa2eb3ae77428eb83c428c5
  Author: Amara Emerson <amara at apple.com>
  Date:   2021-07-24 (Sat, 24 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Widen non-pow-2 types for shifts before clamping.

For types like s96, we don't want to clamp to s64, we want to first widen to
s128 and then narrow it. Otherwise we end up with impossible to legalize types.