[all-commits] [llvm/llvm-project] 1528a4: [llvm][sve] Lowering for VLS truncating stores

[David Truby via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1528a4d40022925dcc3e8cb6b8af7dd109ad7075
      https://github.com/llvm/llvm-project/commit/1528a4d40022925dcc3e8cb6b8af7dd109ad7075
  Author: David Truby <david.truby at arm.com>
  Date:   2021-07-23 (Fri, 23 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AMDGPU/R600ISelLowering.h
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    A llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
    M llvm/test/CodeGen/Mips/cconv/byval.ll
    M llvm/test/CodeGen/Mips/cconv/vector.ll
    M llvm/test/CodeGen/Mips/llvm-ir/store.ll

  Log Message:
  -----------
  [llvm][sve] Lowering for VLS truncating stores

This adds custom lowering for truncating stores when operating on
fixed length vectors in SVE. It also includes a DAG combine to
fold extends followed by truncating stores into non-truncating
stores in order to prevent this pattern appearing once truncating
stores are supported.

Currently truncating stores are not used in certain cases where
the size of the vector is larger than the target vector width.

Differential Revision: https://reviews.llvm.org/D104471