[all-commits] [llvm/llvm-project] 1cda1e: [ARC] Add disassembly for the conditioned RSUB imm...

[Thomas Johnson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1cda1e618648d463f89eb5cea8c9849bc0074b24
      https://github.com/llvm/llvm-project/commit/1cda1e618648d463f89eb5cea8c9849bc0074b24
  Author: Thomas Johnson <thomasj at synopsys.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M llvm/lib/Target/ARC/ARCInstrFormats.td
    M llvm/lib/Target/ARC/ARCInstrInfo.td
    M llvm/test/MC/Disassembler/ARC/alu.txt
    M llvm/test/MC/Disassembler/ARC/misc.txt

  Log Message:
  -----------
  [ARC] Add disassembly for the conditioned RSUB immediate instruction

Differential Revision: https://reviews.llvm.org/D106497