[all-commits] [llvm/llvm-project] 8d8656: [RegisterCoalescer] Make resolveConflicts aware of...

[ShihPo Hung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d86562e5f1f0bddb0a1e35c46577046530adadb
      https://github.com/llvm/llvm-project/commit/8d86562e5f1f0bddb0a1e35c46577046530adadb
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir

  Log Message:
  -----------
  [RegisterCoalescer] Make resolveConflicts aware of earlyclobber

Prior to this patch, it skipped the instruction defining VNI when checking if the tainted lanes are used.
In the given example, VRGATHER is an illegal instruction because its DstReg overlaps with SrcReg.

Therefore we need to check the defining instruction as well when there is an earlyclobber constraint.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D105684