[all-commits] [llvm/llvm-project] a9de8f: [Clang][RISCV] Implement vlsseg.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9de8f7a5391310ddb310411cbb999d99bfd026d
      https://github.com/llvm/llvm-project/commit/a9de8f7a5391310ddb310411cbb999d99bfd026d
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c

  Log Message:
  -----------
  [Clang][RISCV] Implement vlsseg.

Differential Revision: https://reviews.llvm.org/D103796


  Commit: 1c55033ea16f208b08606c10c7c185c9598a6c7e
      https://github.com/llvm/llvm-project/commit/1c55033ea16f208b08606c10c7c185c9598a6c7e
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c

  Log Message:
  -----------
  [Clang][RISCV] Implement vloxseg and vluxseg.

Differential Revision: https://reviews.llvm.org/D103809


  Commit: e08825b0fc6e816b928542fcd7be2216d52f2c30
      https://github.com/llvm/llvm-project/commit/e08825b0fc6e816b928542fcd7be2216d52f2c30
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c

  Log Message:
  -----------
  [Clang][RISCV] Add vloxseg and vluxseg test cases.


  Commit: d1a401b35b2991fb8490fa4e312fc730077e0d34
      https://github.com/llvm/llvm-project/commit/d1a401b35b2991fb8490fa4e312fc730077e0d34
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c

  Log Message:
  -----------
  [Clang][RISCV] Implement vsseg.

Differential Revision: https://reviews.llvm.org/D103871


  Commit: 915e6dc09cd008d15c80b57c4922086184b29f3c
      https://github.com/llvm/llvm-project/commit/915e6dc09cd008d15c80b57c4922086184b29f3c
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c

  Log Message:
  -----------
  [Clang][RISCV] Implement vssseg.

Differential Revision: https://reviews.llvm.org/D103872


  Commit: 698f288fa16ca22e10d11f11f57441940e468908
      https://github.com/llvm/llvm-project/commit/698f288fa16ca22e10d11f11f57441940e468908
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-07-22 (Thu, 22 Jul 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c

  Log Message:
  -----------
  [Clang][RISCV] Implement vsoxseg and vsuxseg.

Differential Revision: https://reviews.llvm.org/D103873


Compare: https://github.com/llvm/llvm-project/compare/9dcd75f86f24...698f288fa16c