[all-commits] [llvm/llvm-project] 291e0d: AArch64: support 8 & 16-bit atomic operations in G...

[Tim Northover via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 291e0daa6ed658a92a0adbf2a8bba5ca02560b93
      https://github.com/llvm/llvm-project/commit/291e0daa6ed658a92a0adbf2a8bba5ca02560b93
  Author: Tim Northover <t.p.northover at gmail.com>
  Date:   2021-07-21 (Wed, 21 Jul 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir

  Log Message:
  -----------
  AArch64: support 8 & 16-bit atomic operations in GlobalISel

We have SelectionDAG patterns for 8 & 16-bit atomic operations, but they
assume the value types will have been legalized to 32-bits. So this adds
the ability to widen them to both AArch64 & generic GISel
infrastructure.


  Commit: 19d2e42be2cd586456ae03374b5fd3e22d9d14f2
      https://github.com/llvm/llvm-project/commit/19d2e42be2cd586456ae03374b5fd3e22d9d14f2
  Author: Tim Northover <t.p.northover at gmail.com>
  Date:   2021-07-21 (Wed, 21 Jul 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMFrameLowering.cpp
    M llvm/test/CodeGen/ARM/tailcc-call.ll

  Log Message:
  -----------
  ARM: don't return by popping PC if we have to adjust the stack afterwards.

In mandatory tail calling conventions we might have to deallocate stack
space used by our arguments before return. This happens after popping
CSRs, so the pop cannot be turned into the return itself in this case.

The else branch here was already a nop, so removing it as a tidy-up.


Compare: https://github.com/llvm/llvm-project/compare/2d80bbd939dc...19d2e42be2cd