[all-commits] [llvm/llvm-project] 1a6dc9: [PowerPC] Inefficient register allocation of ACC r...

[stefanp-ibm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a6dc92be7d68611077f0fb0b723b361817c950c
      https://github.com/llvm/llvm-project/commit/1a6dc92be7d68611077f0fb0b723b361817c950c
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2021-07-20 (Tue, 20 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/test/CodeGen/PowerPC/mma-outer-product.ll
    M llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
    M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

  Log Message:
  -----------
  [PowerPC] Inefficient register allocation of ACC registers results in many copies.

ACC registers are a combination of four consecutive vector registers.
If the vector registers are assigned first this often forces a number
of copies to appear just before the ACC register is created. If the ACC
register is assigned first then fewer copies are generated when the vector
registers are assigned.

This patch tries to force the register allocator to assign the ACC registers first
and then the UACC registers and then the vector pair registers. It does this
by changing the priority of the register classes.

This patch also adds hints to help the register allocator assign UACC registers from
known ACC registers and vector pair registers from known UACC registers.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D105854