[all-commits] [llvm/llvm-project] 4f1270: [RISCV] Add test cases to show an issue with our f...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f1270a61e15fc43b8467885254f7246b4b75b71
      https://github.com/llvm/llvm-project/commit/4f1270a61e15fc43b8467885254f7246b4b75b71
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-19 (Mon, 19 Jul 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll

  Log Message:
  -----------
  [RISCV] Add test cases to show an issue with our fcvt.wu isel patterns on RV64.

The pattern we match is (sext_inreg (assertzexti32 (fp_to_uint)), i32). If
the assertzexti32 has an additional user we'll end up emitting
an fcvt.wu and an fcvt.lu.

This can happen if the original fp_to_uint before type legalization
has one user that causes a sext_inreg to be emitted and one that
doesn't.