[all-commits] [llvm/llvm-project] 5561ad: [ARM] Remove PromotedBitwiseVT for NEON types

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5561ad8b3632ec6ec4ca079e4b396fa6a8944f09
      https://github.com/llvm/llvm-project/commit/5561ad8b3632ec6ec4ca079e4b396fa6a8944f09
  Author: David Green <david.green at arm.com>
  Date:   2021-07-19 (Mon, 19 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrNEON.td
    M llvm/test/CodeGen/ARM/vector-promotion.ll
    M llvm/test/CodeGen/ARM/vmov.ll

  Log Message:
  -----------
  [ARM] Remove PromotedBitwiseVT for NEON types

This removes the promotion of NEON AND, OR and XOR nodes to v2i32/v4i32,
treating them the same as the AArch64 and MVE backends where we just add
the relevant patterns for each legal type. This prevents a lot of
bitcasts from being added to the DAG, which have the potential to make
optimizations more difficult. It does mean adding extra patterns, and
some codegen can change due to the types now being legal, not promoted.

Differential Revision: https://reviews.llvm.org/D105588