[all-commits] [llvm/llvm-project] dc0bbc: [IfCvt] Don't use pristine register for counting l...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dc0bbc9d891ab20850761d8d75acc6676754ce2d
      https://github.com/llvm/llvm-project/commit/dc0bbc9d891ab20850761d8d75acc6676754ce2d
  Author: David Green <david.green at arm.com>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/LivePhysRegs.h
    M llvm/lib/CodeGen/IfConversion.cpp
    M llvm/lib/CodeGen/LivePhysRegs.cpp
    A llvm/test/CodeGen/ARM/ldrd_ifcvt.ll

  Log Message:
  -----------
  [IfCvt] Don't use pristine register for counting liveins for predicated instructions.

The test case here hits machine verifier problems. There are volatile
long loads that the results of do not get used, loading into two dead
registers. IfCvt will predicate them and as it does will add implicit
uses of the predicating registers due to thinking they are live in. As
nothing has used the register, the machine verifier disagrees that they
are really live and we end up with a failure.

The registers come from Pristine regs that LivePhysRegs counts as live.
This patch adds a addLiveInsNoPristines method to be used instead in
IfCvt, so that only really live in regs need to be added as implicit
operands.

Differential Revision: https://reviews.llvm.org/D90965