[all-commits] [llvm/llvm-project] 86109f: [RISCV] Add test cases for div/rem with constant l...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 86109fa9e84cd6630f5f14414779b890144b3fc3
      https://github.com/llvm/llvm-project/commit/86109fa9e84cd6630f5f14414779b890144b3fc3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-10 (Sat, 10 Jul 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/rem.ll

  Log Message:
  -----------
  [RISCV] Add test cases for div/rem with constant left hand side. NFC

Some of these would produce better code if we used W instructions,
but constant LHS currently prevents that.