[all-commits] [llvm/llvm-project] c2b7f0: [SLP] make invalid operand explicit for extra arg ...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c2b7f09d8c276c83f3af5123a0ca55d62b0ffaab
      https://github.com/llvm/llvm-project/commit/c2b7f09d8c276c83f3af5123a0ca55d62b0ffaab
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-07-09 (Fri, 09 Jul 2021)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

  Log Message:
  -----------
  [SLP] make invalid operand explicit for extra arg in reduction matching; NFC

This makes it clearer when we have encountered the extra arg.
Also, we may need to adjust the way the operand iteration
works when handling logical and/or.


  Commit: 86e65234404fa329cd65b5522aae8e82f4fa152b
      https://github.com/llvm/llvm-project/commit/86e65234404fa329cd65b5522aae8e82f4fa152b
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-07-09 (Fri, 09 Jul 2021)

  Changed paths:
    A llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll

  Log Message:
  -----------
  [SLP] add tests for poison-safe logical reductions; NFC


  Commit: 55c5c0485924895800c683386a4560bdc253623e
      https://github.com/llvm/llvm-project/commit/55c5c0485924895800c683386a4560bdc253623e
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-07-09 (Fri, 09 Jul 2021)

  Changed paths:
    A llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll

  Log Message:
  -----------
  [PhaseOrdering] add tests for vector cmp reductions; NFC

These are based on PR41312. There needs to be effort
from all of SimplifyCFG, InstCombine, SLP, and possibly
VectorCombine to get this into ideal form.


Compare: https://github.com/llvm/llvm-project/compare/f8bef4734845...55c5c0485924