[all-commits] [llvm/llvm-project] 88326b: [RISCV][clang] Add macro __riscv_zvlsseg for RVV Z...

[Ben Shi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88326bbce38c53f4782ba3b593b6720438a9569c
      https://github.com/llvm/llvm-project/commit/88326bbce38c53f4782ba3b593b6720438a9569c
  Author: jacquesguan <Jianjian.Guan at streamcomputing.com>
  Date:   2021-07-09 (Fri, 09 Jul 2021)

  Changed paths:
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins

Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only
with target feature Zvlsseg.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D105626