[all-commits] [llvm/llvm-project] 026bb8: [AArch64][SVE] Add ISel patterns for floating poin...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 026bb84bcd42b875d77b769eb5ee4c19fc2a9719
      https://github.com/llvm/llvm-project/commit/026bb84bcd42b875d77b769eb5ee4c19fc2a9719
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-07-08 (Thu, 08 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fcmp.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-compares.ll

  Log Message:
  -----------
  [AArch64][SVE] Add ISel patterns for floating point compare with zero instructions

Additionally, lower the floating point compare SVE intrinsics to
SETCC_MERGE_ZERO ISD nodes to avoid duplicating ISel patterns.

Differential Revision: https://reviews.llvm.org/D105486