[all-commits] [llvm/llvm-project] 0c1a77: [MLIR] Simplify affine.if having yield values and ...

[Srishti Srivastava via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0c1a7730f5372e862150f313df4d9c44757352f4
      https://github.com/llvm/llvm-project/commit/0c1a7730f5372e862150f313df4d9c44757352f4
  Author: Srishti Srivastava <srishti.srivastava at polymagelabs.com>
  Date:   2021-07-07 (Wed, 07 Jul 2021)

  Changed paths:
    M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
    M mlir/test/Dialect/Affine/simplify-affine-structures.mlir

  Log Message:
  -----------
  [MLIR] Simplify affine.if having yield values and trivial conditions

When an affine.if operation is returning/yielding results and has a
trivially true or false condition, then its 'then' or 'else' block,
respectively, is promoted to the affine.if's parent block and then, the
affine.if operation is replaced by the correct results/yield values.
Relevant test cases are also added.

Signed-off-by: Srishti Srivastava <srishti.srivastava at polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D105418