[all-commits] [llvm/llvm-project] 94e01d: [Hexagon] Generate trap/undef if misaligned access...

[Krzysztof Parzyszek via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 94e01d579c1954bed2dbd2d82a64ff72baf72223
      https://github.com/llvm/llvm-project/commit/94e01d579c1954bed2dbd2d82a64ff72baf72223
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2021-07-06 (Tue, 06 Jul 2021)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.h
    M llvm/test/CodeGen/Hexagon/misaligned-const-load.ll
    M llvm/test/CodeGen/Hexagon/misaligned-const-store.ll

  Log Message:
  -----------
  [Hexagon] Generate trap/undef if misaligned access is detected

This applies to memory accesses to (compile-time) constant addresses
(such as memory-mapped registers). Currently when a misaligned access
to such an address is detected, a fatal error is reported. This change
will emit a remark, and the compilation will continue with a trap,
and "undef" (for loads) emitted.

This fixes https://llvm.org/PR50838.

Differential Revision: https://reviews.llvm.org/D50524