[all-commits] [llvm/llvm-project] 2b5e53: [RISCV] Add support for matching vwmul(u) and vwma...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b5e53111a24eebaa025d12832380638cb0598a1
      https://github.com/llvm/llvm-project/commit/2b5e53111a24eebaa025d12832380638cb0598a1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-07-06 (Tue, 06 Jul 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwacc.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaccu.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

  Log Message:
  -----------
  [RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.

This adds a DAG combine to detect sext/zext inputs and emit a
new ISD opcode. The extends will either be removed or replaced
with narrower extends.

Isel patterns are used to match add and widening mul to vwmacc
similar to the recently added vmacc patterns.

There's still some work to be to match vmulsu.
We should also rewrite splats that were extended as scalars and
then splatted.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D104802