[all-commits] [llvm/llvm-project] c5dfee: [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector ...

[Peter Waller via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c5dfee44b983d7a96f2c1a234f83abf41c7e2443
      https://github.com/llvm/llvm-project/commit/c5dfee44b983d7a96f2c1a234f83abf41c7e2443
  Author: Peter Waller <peter.waller at arm.com>
  Date:   2021-07-06 (Tue, 06 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
    A llvm/test/CodeGen/AArch64/sve-ld1r.ll
    A llvm/test/CodeGen/AArch64/sve-ld1r.mir
    M llvm/test/CodeGen/AArch64/sve-vector-splat.ll

  Log Message:
  -----------
  [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory

This avoids the use of the vector unit for copying from scalar to
vector. There is an extra ptrue instruction, but a predicate register
with the ptrue pattern populated is likely to be free in the context of
real code.

Tests were generated from a template to cover the axes mentioned at the
top of the test file.

Co-authored-by: Francesco Petrogalli <francesco.petrogalli at arm.com>

Differential Revision: https://reviews.llvm.org/D103170