[all-commits] [llvm/llvm-project] d4ed96: [AArch64ISelDAGToDAG] Fix ORRWrs/ORRXrs usefulbits...

[ChenMd via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d4ed965b2d14361e4273525a9888344a25f3800c
      https://github.com/llvm/llvm-project/commit/d4ed965b2d14361e4273525a9888344a25f3800c
  Author: Tiehu Zhang <zhangtiehu at huawei.com>
  Date:   2021-07-06 (Tue, 06 Jul 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    A llvm/test/CodeGen/AArch64/arm64-isel-or.ll

  Log Message:
  -----------
  [AArch64ISelDAGToDAG] Fix ORRWrs/ORRXrs usefulbits calculation bug

For the following case:

    t8: i32 = or t7, t4
    t10: i32 = ORRWrs t8, t8, TargetConstant:i32<73>

Current code wrongly returns (t8 >> shiftConstant) as the
UsefulBits of t8, which in fact is (t8 | (t8 >> shiftConstant)).

Reviewed by: sdesmalen, mdchen

Differential Revision: https://reviews.llvm.org/D102759