[all-commits] [llvm/llvm-project] 266872: [SelectionDAG] Implement PromoteIntRes_INSERT_SUBV...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2668727929e497553eba485876eb6190d38cc367
      https://github.com/llvm/llvm-project/commit/2668727929e497553eba485876eb6190d38cc367
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-07-01 (Thu, 01 Jul 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll

  Log Message:
  -----------
  [SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR

Inserting into a smaller-than-legal scalable vector would result in an
internal compiler error. For example, inserting a <vscale x 4 x i8> into
a <vscale x 8 x i8> (both illegal vector types for SVE) would cause a
crash.

This crash was happening because there was no code to promote (legalise)
the result of an INSERT_SUBVECTOR node.

This patch implements PromoteIntRes_INSERT_SUBVECTOR, which legalises
the ISD node. This is currently done by going through memory. This is
necessary because of the requirement that the SubVec parameter of the
INSERT_SUBVECTOR node must be smaller than the Vec parameter, which
means that INSERT_SUBVECTOR cannot always have a legal result/operand
types.

Co-Authored-by: Joe Ellis <joe.ellis at arm.com>

Differential Revision: https://reviews.llvm.org/D102766