[all-commits] [llvm/llvm-project] fae056: CodeGen: Print/parse LLTs in MachineMemOperands

Wed Jun 30 13:54:42 PDT 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fae05692a36f9ebbd201d93c2a6b0f927564d7e6
      https://github.com/llvm/llvm-project/commit/fae05692a36f9ebbd201d93c2a6b0f927564d7e6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-06-30 (Wed, 30 Jun 2021)

  Changed paths:
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MachineOperand.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/debug-loc-legalize-tail-call.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/labels-are-not-dead.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bzero.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr-debugloc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-store-undef.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir
    M llvm/test/CodeGen/AArch64/aarch64-ldst-modified-baseReg.mir
    M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
    M llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir
    M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
    M llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
    M llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
    M llvm/test/CodeGen/AArch64/branch-folder-merge-mmos.ll
    M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
    M llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
    M llvm/test/CodeGen/AArch64/cfi_restore.mir
    M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
    M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
    M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
    M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
    M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
    M llvm/test/CodeGen/AArch64/falkor-hwpf-fix.mir
    M llvm/test/CodeGen/AArch64/irg-nomem.mir
    M llvm/test/CodeGen/AArch64/jti-correct-datatype.mir
    M llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
    M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
    M llvm/test/CodeGen/AArch64/ldst-miflags.mir
    M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
    M llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
    M llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
    M llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
    M llvm/test/CodeGen/AArch64/ldst-opt.mir
    M llvm/test/CodeGen/AArch64/loh-use-between-adrp-add.mir
    M llvm/test/CodeGen/AArch64/loop-sink-limit.mir
    M llvm/test/CodeGen/AArch64/loop-sink.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-iterative-2.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-iterative.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
    M llvm/test/CodeGen/AArch64/machine-scheduler.mir
    M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
    M llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
    M llvm/test/CodeGen/AArch64/multi-vector-store-size.ll
    M llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
    M llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
    M llvm/test/CodeGen/AArch64/seqpairspill.mir
    M llvm/test/CodeGen/AArch64/settag-merge.mir
    M llvm/test/CodeGen/AArch64/speculation-hardening-sls-blr.mir
    M llvm/test/CodeGen/AArch64/spill-fold.mir
    M llvm/test/CodeGen/AArch64/spill-undef.mir
    M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
    M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
    M llvm/test/CodeGen/AArch64/taildup-inst-dup-loc.mir
    M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
    M llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
    M llvm/test/CodeGen/AArch64/wineh-frame4.mir
    M llvm/test/CodeGen/AArch64/wineh-frame6.mir
    M llvm/test/CodeGen/AArch64/wineh-frame7.mir
    M llvm/test/CodeGen/AArch64/wineh-frame8.mir
    M llvm/test/CodeGen/AArch64/wineh1.mir
    M llvm/test/CodeGen/AArch64/wineh2.mir
    M llvm/test/CodeGen/AArch64/wineh3.mir
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    M llvm/test/CodeGen/AArch64/wineh5.mir
    M llvm/test/CodeGen/AArch64/wineh6.mir
    M llvm/test/CodeGen/AArch64/wineh7.mir
    M llvm/test/CodeGen/AArch64/wineh8.mir
    M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
    M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
    M llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
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    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
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    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
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    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
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    M llvm/test/DebugInfo/X86/single-location-interrupted-scope.mir
    M llvm/test/DebugInfo/X86/single-location.mir
    M llvm/test/MachineVerifier/generic-vreg-undef-use.mir
    M llvm/test/MachineVerifier/test_g_bzero.mir
    M llvm/test/MachineVerifier/test_g_load.mir
    M llvm/test/MachineVerifier/test_g_memcpy.mir
    M llvm/test/MachineVerifier/test_g_memset.mir
    M llvm/test/MachineVerifier/test_g_sextload.mir
    M llvm/test/MachineVerifier/test_g_store.mir
    M llvm/test/MachineVerifier/test_g_zextload.mir
    M llvm/test/MachineVerifier/verify-regops.mir
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
    M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
    M llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
    M llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
    M llvm/unittests/MIR/MachineMetadata.cpp

  Log Message:
  -----------
  CodeGen: Print/parse LLTs in MachineMemOperands

This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.