[all-commits] [llvm/llvm-project] 2da588: [TableGen] Allow identical MnemonicAliases with no...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2da58826a5e0716163d3b91afcde1218a211d714
      https://github.com/llvm/llvm-project/commit/2da58826a5e0716163d3b91afcde1218a211d714
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2021-06-30 (Wed, 30 Jun 2021)

  Changed paths:
    A llvm/test/TableGen/MnemonicAlias.td
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  -----------
  [TableGen] Allow identical MnemonicAliases with no predicate

My use case for this is illustrated in the test case: I want to define
the same instruction twice with different (disjoint) predicates, because
the instruction has different operands on different subtargets. It's
convenient to do this with a multiclass that also defines an alias for
the instruction.

Previously tablegen would complain if this alias was defined twice with
no predicate. One way to fix this would be to add a predicate on each
definition of the alias, matching the predicate on the instruction. But
this (a) is slightly awkward to do in the real world use case I had, and
(b) leads to an inefficient matcher that will do something like this:

  if (Mnemonic == "foo_alias") {
    if (Features.test(Feature_Subtarget1Bit))
      Mnemonic == "foo";
    else if (Features.test(Feature_Subtarget2Bit))
      Mnemonic == "foo";
    return;
  }

It would be more efficient to skip the feature tests and return "foo"
unconditionally.

Overall it seems better to allow multiple definitions of the identical
alias with no predicate.

Differential Revision: https://reviews.llvm.org/D105033