[all-commits] [llvm/llvm-project] 3b6dfa: [RISCV] Protect the SHL/SRA/SRL handlers in LowerO...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b6dfa381edfc66864cfd6dbc2769ba645858120
      https://github.com/llvm/llvm-project/commit/3b6dfa381edfc66864cfd6dbc2769ba645858120
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-29 (Tue, 29 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll

  Log Message:
  -----------
  [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being called for an illegal i32 shift amount.

It seems it is possible for DAG combine to create a shl with an
i64 result type and an i32 shift amount. This is ok before type
legalization since the type don't need to match in SelectionDAG.
This results in type legalization calling LowerOperation to
legalize just the amount. We weren't expecting this so we
asserted for not finding a fixed vector shift.

To fix this, I've added a check for the fixed vector case and
returned SDValue() to get the default type legalizer. I've
factored all shifts together and added a fixed vector specific
handler to avoid repeating similar code for each in
LowerOperation.

The particular case I found was exposed by D104581, but the bad
shift is created after that patch triggers.