[all-commits] [llvm/llvm-project] f9f5d4: [AMDGPU][GlobalISel] Legalize and select G_SBFX an...

[bcahoon via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9f5d415453b3fee98817d4f0bd8e5b5415e34cc
      https://github.com/llvm/llvm-project/commit/f9f5d415453b3fee98817d4f0bd8e5b5415e34cc
  Author: Brendon Cahoon <brendon.cahoon at amd.com>
  Date:   2021-06-28 (Mon, 28 Jun 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX

Adds legalizer, register bank select, and instruction
select support for G_SBFX and G_UBFX. These opcodes generate
scalar or vector ALU bitfield extract instructions for
AMDGPU. The instructions allow both constant or register
values for the offset and width operands.

The 32-bit scalar version is expanded to a sequence that
combines the offset and width into a single register.

There are no 64-bit vgpr bitfield extract instructions, so the
operations are expanded to a sequence of instructions that
implement the operation. If the width is a constant,
then the 32-bit bitfield extract instructions are used.

Moved the AArch64 specific code for creating G_SBFX to
CombinerHelper.cpp so that it can be used by other targets.
Only bitfield extracts with constant offset and width values
are handled currently.

Differential Revision: https://reviews.llvm.org/D100149