[all-commits] [llvm/llvm-project] 81b2f9: [RISCV] Use zexti32/sexti32 in srliw/sraiw isel pa...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81b2f95971edd47a0057ac4a77b674d7ea620c01
      https://github.com/llvm/llvm-project/commit/81b2f95971edd47a0057ac4a77b674d7ea620c01
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-26 (Sat, 26 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/alu8.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

  Log Message:
  -----------
  [RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions.