[all-commits] [llvm/llvm-project] d4f4a1: [RISCV] Add DAG combine to detect opportunities to...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d4f4a1ba626d7c3e4442d6f68feb79d56eba9601
      https://github.com/llvm/llvm-project/commit/d4f4a1ba626d7c3e4442d6f68feb79d56eba9601
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-25 (Fri, 25 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/aext-to-sext.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to detect opportunities to replace (i64 (any_extend (i32 X)) with sign_extend.

If type legalization is going to insert a sign_extend for other users
of X and we can fold the sign_extend into ADDW/MULW/SUBW, it is
better to replace the ANY_EXTEND so we don't end up with a separate
ADD/MUL/SUB instruction for the users of the ANY_EXTEND.

I'm only handling setcc uses right now, but there are other
instructions that force sign_extends like ashr.

There are probably other *W instructions we could use in addition
to ADDW/SUBW/MULW.

My motivating case was a loop terminating compare and a phi use
as seen in the new test file.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D104581