[all-commits] [llvm/llvm-project] 51e434: [AArch64] Custom lower <4 x i8> loads

[sjoerdmeijer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51e434fc2590d1d3ffa6545cd07290a238db2b88
      https://github.com/llvm/llvm-project/commit/51e434fc2590d1d3ffa6545cd07290a238db2b88
  Author: Sjoerd Meijer <sjoerd.meijer at arm.com>
  Date:   2021-06-25 (Fri, 25 Jun 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll
    R llvm/test/CodeGen/AArch64/neon-extload.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/usub_sat_vec.ll

  Log Message:
  -----------
  [AArch64] Custom lower <4 x i8> loads

This custom lowers <4 x i8> vector loads using a 32-bit load, followed by 2
SSHLL instructions to extend it to e.g. a <4 x i32> vector. Before, it was
really inefficient and expensive to construct a <4 x i32> for this as 4 byte
loads and 4 moves were used. With this improvement SLP vectorisation might for
example become profitable, see D103629.

Differential Revision: https://reviews.llvm.org/D104782