[all-commits] [llvm/llvm-project] b6ff4d: [PowerPC] Handle FP physical register in inline as...

[Sean Fertile via All-commits]

  Branch: refs/heads/release/12.x
  Home:   https://github.com/llvm/llvm-project
  Commit: b6ff4dd2e99e86390321fdd43a22c93d0659fe2a
      https://github.com/llvm/llvm-project/commit/b6ff4dd2e99e86390321fdd43a22c93d0659fe2a
  Author: Sean Fertile <sd.fertile at gmail.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    A llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll
    A llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr.ll

  Log Message:
  -----------
  [PowerPC] Handle FP physical register in inline asm constraint.

Do not defer to the base class when the register constraint is a
physical fpr. The base class will select SPILLTOVSRRC as the register
class and register allocation will fail on subtargets without VSX
registers.

Differential Revision: https://reviews.llvm.org/D91629

(cherry picked from commit 4e127bce2d1133ba95a551d69bd0e8fc3b4f9e71)