[all-commits] [llvm/llvm-project] f22536: [RISCV] Add vget/vset intrinsics for inserting and...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f225367305c82ce391bb470f735b19e924ff7372
      https://github.com/llvm/llvm-project/commit/f225367305c82ce391bb470f735b19e924ff7372
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/lib/Sema/SemaChecking.cpp
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

  Log Message:
  -----------
  [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D104822