[all-commits] [llvm/llvm-project] 6b0f98: [ValueTypes] Define MVTs for v3i64/v3f64 to comple...

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b0f98d442e0cf2b6e3a20ba518abb5549aa4999
      https://github.com/llvm/llvm-project/commit/6b0f98d442e0cf2b6e3a20ba518abb5549aa4999
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  [ValueTypes] Define MVTs for v3i64/v3f64 to complement v6i32/v6f32

Having type symmetry with these is somewhat necessary when implementing support for 192-bit values.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104621


  Commit: 98f48723f2ca286d6f12bb0c4dc7830a55e85637
      https://github.com/llvm/llvm-project/commit/98f48723f2ca286d6f12bb0c4dc7830a55e85637
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

  Log Message:
  -----------
  [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs

Add SReg_224, VReg_224, AReg_224, etc.
Link 224-bit types with v7i32/v7f32.
Link existing 192-bit types to newly added v3i64/v3f64/v6i32/v6f32.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D104622


Compare: https://github.com/llvm/llvm-project/compare/82e03e494f98...98f48723f2ca