[all-commits] [llvm/llvm-project] 913195: [CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchI...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 91319534ba00910fc8027dc4be3eeea4c321621d
      https://github.com/llvm/llvm-project/commit/91319534ba00910fc8027dc4be3eeea4c321621d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-23 (Wed, 23 Jun 2021)

  Changed paths:
    M llvm/lib/CodeGen/CodeGenPrepare.cpp
    M llvm/test/CodeGen/RISCV/jumptable.ll

  Log Message:
  -----------
  [CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt.

This optimization pre-promotes the input and constants for a
switch instruction to a legal type so that all the generated compares
share the same extend. Since RISCV prefers sext for i32 to i64
extends, we should honor that to use sext.w instead of a pair
of shifts.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D104612