[all-commits] [llvm/llvm-project] a37cf1: [RISCV] Add explicit copy to V0 in the masked vmsg...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a37cf17834d39411ed1d669098b428f8374c5b45
      https://github.com/llvm/llvm-project/commit/a37cf17834d39411ed1d669098b428f8374c5b45
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-23 (Wed, 23 Jun 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.

This is consistent with our other masked vector instructions.
Previously we found cases where not doing this broke fast reg
alloc.