[all-commits] [llvm/llvm-project] 36111f: [TableGen] Fix printing second PC-relative operand

[Igor Kudrin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36111f28edb1182273c6409c3fb7808e0e9cbd60
      https://github.com/llvm/llvm-project/commit/36111f28edb1182273c6409c3fb7808e0e9cbd60
  Author: Igor Kudrin <ikudrin at accesssoftek.com>
  Date:   2021-06-23 (Wed, 23 Jun 2021)

  Changed paths:
    A llvm/test/TableGen/AsmWriterPCRelOp.td
    M llvm/utils/TableGen/AsmWriterInst.h

  Log Message:
  -----------
  [TableGen] Fix printing second PC-relative operand

If an instruction has several operands and a PC-relative one is not the
first of them, the generator may produce the code that does not pass the
'Address' parameter to the printout method. For example, for an Arm
instruction 'LE LR, $imm', it reuses the same code as for other
instructions where the second operand is not PC-relative:

void ARMInstPrinter::printInstruction(...) {
...
  case 11:
    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, ...
    printOperand(MI, 1, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    break;
...

The patch fixes that by considering 'PCRel' when comparing
'AsmWriterOperand' values.

Differential Revision: https://reviews.llvm.org/D104698