[all-commits] [llvm/llvm-project] d03736: [MCA] [In-order pipeline] Fix for 0 latency instru...

[Patrick Holland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d03736455ceeeb8ce639b65b4965436297cf24a4
      https://github.com/llvm/llvm-project/commit/d03736455ceeeb8ce639b65b4965436297cf24a4
  Author: Patrick Holland <patrickeholland at gmail.com>
  Date:   2021-06-22 (Tue, 22 Jun 2021)

  Changed paths:
    M llvm/lib/MCA/Stages/InOrderIssueStage.cpp
    M llvm/tools/llvm-mca/Views/TimelineView.cpp

  Log Message:
  -----------
  [MCA] [In-order pipeline] Fix for 0 latency instruction causing assertion to fail.

0 latency instructions now get processed and retired properly within the in-order pipeline. Had to fix a bug within TimelineView.cpp as well that would show up when a 0 latency instruction was the first instruction in the source.

Differential Revision: https://reviews.llvm.org/D104675