[all-commits] [llvm/llvm-project] 399631: [DAGCombine] reassoc flag shouldn't enable contract

[jsji via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3996311ee1b0a3c29a3ffcf9400e12ca76a846d9
      https://github.com/llvm/llvm-project/commit/3996311ee1b0a3c29a3ffcf9400e12ca76a846d9
  Author: Jinsong Ji <jji at us.ibm.com>
  Date:   2021-06-21 (Mon, 21 Jun 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/fadd-combines.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
    M llvm/test/CodeGen/PowerPC/combine-fneg.ll
    M llvm/test/CodeGen/PowerPC/fdiv.ll
    M llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll
    M llvm/test/CodeGen/PowerPC/fma-assoc.ll
    M llvm/test/CodeGen/PowerPC/fma-combine.ll
    M llvm/test/CodeGen/PowerPC/fma-mutate.ll
    M llvm/test/CodeGen/PowerPC/fma-negate.ll
    M llvm/test/CodeGen/PowerPC/fma-precision.ll
    M llvm/test/CodeGen/PowerPC/fmf-propagation.ll
    M llvm/test/CodeGen/PowerPC/machine-combiner.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll
    M llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
    M llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll
    M llvm/test/CodeGen/X86/machine-combiner.ll
    M llvm/test/CodeGen/X86/sqrt-fastmath.ll

  Log Message:
  -----------
  [DAGCombine] reassoc flag shouldn't enable contract

According to IR LangRef, the FMF flag:

contract
Allow floating-point contraction (e.g. fusing a multiply followed by an
addition into a fused multiply-and-add).

reassoc
Allow reassociation transformations for floating-point instructions.
This may dramatically change results in floating-point.

My understanding is that these two flags shouldn't imply each other,
as we might have a SDNode that can be reassociated with others, but
not contractble.

eg: We may want following fmul/fad/fsub to freely reassoc, but don't
want fma being generated here.

   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub reassoc double %H, %E         ; <double> [#uses=1]

Before https://reviews.llvm.org/D45710, `reassoc` flag actually
did not imply isContratable either.

The current implementation also only check the flag in fadd node,
ignoring fmul node, this patch update that as well.

Reviewed By: spatel, qiucf

Differential Revision: https://reviews.llvm.org/D104247